SH7763 Datasheet, PDF (1103/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
Bit
Bit Name Initial Value R/W Description
4
OBPC
0
R/W Override Bus Pin Control
When this bit is set to 1, the FSDA and FSCL
bits in this register control SDA and SCL
directly. This mode is used for testing purposes
only.
3
MIE
0
R/W Master Interface Enable
When this bit is set to 1, the master interface is
enabled.
2
TSBE
0
R/W Start Byte Transmission Enable
When this bit is set to 1, the master transmit is
issuing a start byte (01H) on the bus after. The
start byte is used for interfacing to slower
microcontroller compatible with I²C bus
interfaces.
1
FSB
0
R/W Forced Stop onto the Bus
When this bit is set to 1, the master transmits a
STOP condition on the bus at the end of the
current transfer. If ESG is also set, the master
immediately transmits a START condition and
begins transmitting a new data packet. If ESG
is not set, state the master enters the idle
state.
0
ESG
0
R/W Enable Start Generation
When this bit is set to 1, the master starts
transmission of a data packet. If the bus is idle
when ESG is set, the master transmits a
START condition on the bus and then
transmits the slave address. If the master is
transferring data when ESG is set, at the end
of that data byte transfer, the master transmits
a repeated START condition before
transmitting the slave address. When
transmitting a data packet, the software must
reset this bit when the slave address has been
transmitted, otherwise a repeated START
condition is transmitted after every
transmission is completed.
Rev. 1.00 Oct. 01, 2007 Page 1037 of 1956
REJ09B0256-0100