SH7763 Datasheet, PDF (1660/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
Bit
Bit Name Initial Value R/W Description
12
DPOL
0
R/W Display Data Polarity Select
Selects the polarity of the LCD_D (display data) for
the LCD module. This bit supports inversion of the
LCD module.
0: LCD_D is high active, transparent-type LCD panel
1: LCD_D is low active, reflective-type LCD panel
11

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
MCNT
0
R/W M Signal Control
Sets whether or not to output the LCD's current-
alternating signal of the LCD module.
0: M (AC line modulation) signal is output
1: M signal is not output
9
CL1CNT 0
R/W CL1 (Horizontal Sync Signal) Control
Sets whether or not to enable CL1 output during the
vertical retrace period.
0: CL1 is output during vertical retrace period
1: CL1 is not output during vertical retrace period
8
CL2CNT 1
R/W CL2 (Dot Clock of LCD Module) Control
Sets whether or not to enable CL2 output during the
vertical and horizontal retrace period.
0: CL2 is output during vertical and horizontal retrace
period
1: CL2 is not output during vertical and horizontal
retrace period
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1594 of 1956
REJ09B0256-0100