SH7763 Datasheet, PDF (380/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 10 SuperHyway Bus Bridge (SBR)
10.2 Register Descriptions
Table 10.1 shows the SBR register configuration. Table 10.2 shows the register state in each
operating mode.
Table 10.1 Register Configuration
Register Name
Area P4
Abbreviation R/W Address*
Area 7
Address*
Access
Size
Bus arbitration priority level
setting register
SBRIVCLV R/W H'FF40 0010 H'1F40 0010 32
SuperHyway bus priority
control register
PRPRICR R/W H'FE60 0018 H'1F60 0018 32
Note: The area P4 address is the address when the P4 area of a virtual address space is used.
The area 7 address is the address when the register is accessed through area 7 of a
physical address space by using the TLB.
Table 10.2 Register State in Each Operating Mode
Register Name
Bus arbitration priority level
setting register
SuperHyway bus priority
control register
Power-On Manual
Abbreviation Reset
Reset
Sleep Standby
SBRIVCLV H'0000 0000 H'0000 0000 Retained Retained
PRPRICR H'0000 0001 H'0000 0001 Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 314 of 1956
REJ09B0256-0100