SH7763 Datasheet, PDF (1025/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Figure 23.9 shows the status change of the E-MAC transmitter. This operation is common among
port 0 and port 1.
1. When the TE bit in ECMR is set, the transmitter enters the transmit idle state.
2. When a transmit request is issued by the transmit E-DMAC, the E-MAC sends the preamble to
GMII/MII/RMII after a transmission delay caused by the carrier detection and frame interval
time. If full-duplex transfer is selected, which does not require carrier detection, the preamble
is sent as soon as a transmit request is issued by the E-DMAC.
3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the
transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the
carrier-not-detected state occurs during data transmission, these are reported as interrupt
sources.
4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is
more transmit data, continues transmitting.
Rev. 1.00 Oct. 01, 2007 Page 959 of 1956
REJ09B0256-0100