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SH7763 Datasheet, PDF (516/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series | |||
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Section 13 PCI Controller (PCIC)
⢠Exclusive access (target only)
 Once locked, only accessible from the device that accessed the LOCK signal
 The SuperHyway bus in not locked during lock transfer
⢠Can support cache coherency between a device connected to the PCI bus and system memory
(PCI target) although device performance may become suboptimal
⢠Supports four external interrupt inputs (INTD to INTA) in host bus bridge mode
⢠Supports one external interrupt output (INTA) in normal mode
⢠Supports both big endian and little endian formats for the SuperHyway bus (the PCI bus
operates in the little endian format)
⢠Number of devices which can be connected
 33 MHz: 4 or less
 66 MHz: 1
The PCIC does not support the following PCI functions.
⢠Cache support (no SBO or SDONE pin)
⢠Address wrap-around mechanism
⢠PCI JTAG (other modules in this LSI can support the JTAG feature)
⢠Dual address cycles
⢠Interrupt acknowledge cycles
⢠Fast back-to-back transfer initiation (supported when performed as a target device)
⢠Extended ROM for initialization and system boot
etc.
Note: When the ratio of the clocks (SHwy clock : PCICLK clock) is in the ranges of (2.1 : 1) to
(3.3 : 1), the PCIC cannot be used.
Rev. 1.00 Oct. 01, 2007 Page 450 of 1956
REJ09B0256-0100
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