SH7763 Datasheet, PDF (1377/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
Initial
Bit
Bit Name Value R/W Description
0
BTIE
0
R/W Multiblock Transfer End Flag Enable.
0: Disables multiblock transfer end flag setting
1: Enables multiblock transfer end flag setting
• INTCR1
Bit: 7
6
5
4
3
2
1
0
INTRQ2E INTRQ1E INTRQ0E — WRERIE CRCERIE DTERIE CTERIE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
INTRQ2E 0
R/W ERR Interrupt Enable
0: Disables ERR interrupt.
1: Enables ERR interrupt.
6
INTRQ1E 0
R/W TRAN Interrupt Enable
0: Disables TRAN interrupt.
1: Enables TRAN interrupt.
5
INTRQ0E 0
R/W FSTAT Interrupt Enable
0: Disables FSTAT interrupt.
1: Enables FSTAT interrupt.
4
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
WRERIE 0
R/W Write Error Flag Enable
0: Disables write error flag setting.
1: Enables write error flag setting.
2
CRCERIE 0
R/W CRC Error Flag Enable
0: Disables CRC error flag setting.
1: Enables CRC error flag setting.
1
DTERIE 0
R/W Data Timeout Error Flag Enable
0: Disables data timeout error flag setting.
1: Enables data timeout error flag setting.
Rev. 1.00 Oct. 01, 2007 Page 1311 of 1956
REJ09B0256-0100