SH7763 Datasheet, PDF (700/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 Clock Pulse Generator (CPG)
A block diagram of the CPG is shown in figure 16.1.
PLL cicuit 3
×̐
Divider 2
Ê·1/4
XTAL
EXTAL
Crystal
oscillator
MD8
PLL circuit 1
Ê·16
Divider 1
Ê·1/4
Ê·1/6
Ê·1/8
Ê·1/12
Ê·1/16
Ê·1/24
DDR clock
Ê¢DDRck0Ê£
Ê¢DDRck90Ê£
Ê¢DDRck180Ê£
Ê¢DDRck270Ê£
PLL circuit 2
×1
CLKOUT
Bus clock
ʢBckʣ
CPU clock
ʢIckʣ
SHwy clock
ʢSHckʣ
Pwripheral clock
ʢPck0ɺPck1ʣ
MD2
MD1
MD0
Clock frequency
controller
FRQCR
Clock controller
STBCR
PLLCR
MSTPCR
Bus interface
Peripheral bus
[Legend]
FRQCR É¿Frequency control register
STBCR É¿Standby control register
MSTPCRÉ¿Module stop register
PLLCR É¿PLL control register
Note : Refer to section 18, Power-Down Mode, for detaiis on STBCR and MSTPCR.
Figure 16.1 Block Diagram of CPG
Rev. 1.00 Oct. 01, 2007 Page 634 of 1956
REJ09B0256-0100