SH7763 Datasheet, PDF (1114/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
S SLAVE ADDRESS R/W A DATA A/A Sr SLAVE ADDRESS R/W A DATA A/A P
Read or Write
(n BYTES
+ ACK)*
Read or Write
(n BYTES
+ ACK)*
Sr = Repeated start condition Direction pf transfer
may change at this point
Notes: 1. Tramsfer dorection of data and acknowledge bits depends on R/W bits.
2. Repeated START condition: Tramsfer is started whrn the I2C_SDL signal is driven high and the I2C_SDA signal is
driven low.
Figure 26.5 Combination Transfer Format of Master Transfer
26.4.7 10-Bit Address Format
Description is given below on the 10-bit address transfer format supported in master mode.
This format has three transfer methods as the 7-bit address transfer format.
Figure 26.6 shows the data transmit format. The set value in the master address register is output
in one byte following the first START condition (S). The value set in the transmit data register
(TXD) is transmitted as a slave address in the second byte. Data on and after the third byte is
transferred in the same way as the 7-bit address data.
11110XX
S SLAVE ADDRESS
R/W A1 SLAVE ADDRESS A2 DATA A DATA
A/A P
1st Byte, 7 Bits
0(Write)
2nd Byte
Data transferred
(n Bytes + ACKNOWLEDGE)
Figure 26.6 10-Bit Address Data Transmit Format
Figure 26.7 shows the data receive format. Two bytes of an address is transmitted a repeated
START in the same way as in the data transmit format. Then, repeated START condition (Sr) is
transmitted and the value set in the address register is output. At this time, STM1 must be set to 1
(receive mode). Data is transferred in the same way as in the 7-bit address data receive format.
Rev. 1.00 Oct. 01, 2007 Page 1048 of 1956
REJ09B0256-0100