SH7763 Datasheet, PDF (1408/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
(6) Commands with Write Data
Flash memory operation commands include a number of commands involving write data. Such
commands confirm the card status through the command argument and command response, and
transmit card information and flash memory data via the MMC_DAT pin. For a command that is
related to time-consuming processing such as flash memory write, the card indicates the data busy
state to the MMC_DAT pin.
In multiblock transfer, there are two methods of transfer: the open-ended and pre-defined methods.
The open-ended method suspends operation at each block transfer and waits for an instruction as
to whether to continue the command sequence. The pre-defined method starts transferring with the
block number set beforehand.
When the FIFO is empty between blocks in multiblock transfer, the command sequence is
suspended. Once the command sequence is suspended, any necessary processing of data in FIFO
must be done before the command sequence is continued.
Figures 31.13 to 31.15 show examples of the command sequence for commands with write data.
Figures 31.16 to 31.18 show the operational flows for commands with write data.
• Create settings to issue a command, and clear FIFO.
• Set the START bit in CMDSTRT to 1 to start command transmission.
• The command response is received from the card.
• If the card returns no command response, the command response is detected through the
command timeout error (CTERI).
• Set the write data to FIFO.
• Set the DATAEN bit in OPCR to 1 to start write data transmission.
• Inter-block suspension in multiblock transfer and suspension by the FIFO empty are detected
through the data response completion flag (DRPI) and FIFO empty flag (FEI), respectively. To
continue the command sequence, fill FIFO with write data and set the DATAEN bit in OPCR
to 1. To end the command sequence, the CMDOFF bit in OPCR should be set to 1 and
CMD12 should be issued. Unless the sequence is suspended in pre-defined multiblock transfer,
CMD12 is not needed.
• The end of the command sequence is detected by poling the BUSY flag in CSTR, data
response completion flag (DRPI), or pre-defined multiblock transfer completion (BTI).
• After the data transfer end (after DPRI detection), the data busy state is checked through
DTBUSY in CSTR. If the card is in the data busy state, the release of the data busy state is
detected through the data busy end flag (DBSYI).
Rev. 1.00 Oct. 01, 2007 Page 1342 of 1956
REJ09B0256-0100