SH7763 Datasheet, PDF (1063/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
Section 25 Stream Interface (STIF)
The stream interface (STIF) transfers stream data between an 8-bit parallel bus and external
memory using general DMAC peripheral module requests (transfer size is fixed at 16 bytes).
25.1 Features
• Number of parallel stream data transfer channels: 2 channels
• Stream data transfer interface
Clock valid reception
Strobe reception
Clock valid transmission
Strobe transmission
• Input/output packet length: 188 or 192 bytes is selectable
The external pin input or peripheral clock 0 (Pck0) can be selected as the stream data transfer
clock source.
• Transmit/receive FIFO size: 768 bytes
• Time stamp adding function
Includes a free-running timer for time stamp.
(The free-running timer input clock can be selected from among 1/2, 1/4, and 1/8 of peripheral
clock 0.)
At reception: The free-running timer value is added to the receive packet as the time stamp
value and stored in memory.
At transmission: A packet is transmitted with the free-running timer value added as the time
stamp value.
• DMA transfer
Data transfer with external memory by means of DMA transfer is supported.
Rev. 1.00 Oct. 01, 2007 Page 997 of 1956
REJ09B0256-0100