SH7763 Datasheet, PDF (1237/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 28.17 Sample Serial Reception Flowchart (2)
In serial reception, the SCIF operates as described below.
1. The SCIF is initialized internally in synchronization with the input or output of the
synchronization clock.
2. The received data is stored in SCRSR in LSB-to-MSB order.
After receiving the data, the SCIF checks whether the receive data can be transferred from
SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an
overrun error is detected in the error check, reception cannot continue.
3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
interrupt (RXI) request is generated.
If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI)
request is generated.
Rev. 1.00 Oct. 01, 2007 Page 1171 of 1956
REJ09B0256-0100