SH7763 Datasheet, PDF (345/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Function
2
SSI2
1
R/W Masks SSI2 interrupts
1
SSI1
1
R/W Masks SSI1 interrupts
0
SECURITY* 1
R/W Masks SECURITY interrupts
Note: * This bit is reserved in the R5S77631.
Description
Masks interrupts for
each peripheral
module.
[When writing]
0: Invalid
1: Interrupts are
masked
[When reading]
0: No mask setting
1: Mask setting
9.3.20 Interrupt Mask Clear Register (INT2MSKCR)
INT2MSKCR is a 32-bit write-only register that clears any masking set in the interrupt mask
register. Setting bits in this register to 1 clears the masking of the corresponding interrupt sources.
Reading bits in this register is always 0.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − − − − − − − ^GPIO
SSI0 MMC
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R R R/W R R/W R/W R R/W R/W R/W R/W R/W
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − − − ^{PCIC1 PCIC0 HAC CMT}
DMAC H-UDI
WDT SCIF1 SCIF0 RTC TMU1 TMU0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R R R R/W R/W R R/W R/W R/W R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 279 of 1956
REJ09B0256-0100