SH7763 Datasheet, PDF (711/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
Section 17 Watchdog Timer and Reset (WDT)
The reset and watchdog timer (WDT) control circuit comprises the reset control unit and WDT
control unit which control the power-on reset sequence and a reset for on-chip peripheral modules
and external devices.
The WDT is a one-channel timer which can be used as the watchdog timer or interval timer.
17.1 Features
• WDT monitors a system crash using a timer counting at specified intervals.
• WDT supports the watchdog timer mode and the interval timer mode.
• WDT generates an internal reset when a WDT overflow occurs in watchdog timer mode.
A power-on reset or a manual reset can be selectable.
• WDT generates the interval timer interrupt when counter overflow occurs in interval timer
mode.
• The maximum time until the watchdog timer overflows is approximately 21 seconds (when the
peripheral clock Pck0 is 50 MHz).
• Writing to WDT-related registers is not normally allowed. A specified code in the upper bits of
write data enables writing to the registers.
Rev. 1.00 Oct. 01, 2007 Page 645 of 1956
REJ09B0256-0100