SH7763 Datasheet, PDF (2022/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Sleep mode ............................................. 678
Slot FPU disable exception..................... 129
Slot illegal instruction exception ............ 127
Smart card interface.............................. 1266
Software standby mode .......................... 679
Stall operations ..................................... 1577
Stream interface (STIF) .......................... 997
Strobe reception.................................... 1019
Strobe transmission .............................. 1023
SuperHyway bus bridge (SBR) .............. 313
System control instructions ...................... 72
System registers........................................ 39
System registers related to FPU................ 39
T
T bit .......................................................... 58
TAP control .......................................... 1823
TCNT Count Timing .............................. 701
TICPI ...................................................... 704
Time setting ............................................ 778
Timer Unit .............................................. 687
Transmission in Master Mode .............. 1229
Transmission in Slave Mode ................ 1231
Transmit Descriptor................................ 939
Transmit/Receive Reset........................ 1233
TUNI ...................................................... 704
TXI ............................................. 1114, 1175
Types of exceptions ................................ 110
U
Unconditional trap .................................. 125
USB function controller (USBF) .......... 1495
User break controller ............................ 1759
User break operation............................. 1782
User debugging interface ...................... 1797
User mode................................................. 38
UTLB...................................................... 156
UTLB address array................................ 175
UTLB data array ..................................... 176
V
Validity bit .............................................. 157
Vector addresses ..................................... 110
Virtual address space .............................. 140
VPN ........................................................ 156
W
Watchdog timer and reset ....................... 645
Write-back instruction ............................ 229
Write-through bit .................................... 158
Rev. 1.00 Oct. 01, 2007 Page 1956 of 1956
REJ09B0256-0100