SH7763 Datasheet, PDF (1342/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
(5) Interrupt Operations
The smart card interface has four types of interrupt requests: transmit data empty interrupt (TXI)
requests, transmit/receive error interrupt (ERI) requests, receive data full interrupt (RXI) requests,
and transmit end interrupt (TEI) requests.
• When the TDRE flag in SCSSR is set to 1, a TXI request is issued.
• When the RDRF flag in SCSSR is set to 1, an RXI request is issued.
• When the ERS, ORER, PER, or WAIT_ER flag in SCSSR is set to 1, an ERI request is issued.
• When the TEND flag in SCSSR is set, a TEI request is issued.
Table 30.6 lists the interrupt sources for the smart card interface. Each of the interrupt requests can
be enabled or disabled using the TIE, RIE, TEIE, and WAIT_IE bits in SCSCR and the EIO bit in
SCSC2R. In addition, each interrupt request can be sent independently to the interrupt controller.
Table 30.6 Interrupt Sources of Smart Card Interface
Operating State
Transmit mode
Normal operation
Receive mode
Error
Normal operation
Error
Flags
TDRE
TEND
ERS
RDRF
ORER, PER
WAIT_ER
Mask Bits
TIE
TEIE
RIE
RIE, EIO
RIE
WAIT_IE
Interrupt Sources
TXI
TEI
ERI
RXI
ERI
ERI
(6) Data Transfer Using DMAC
The smart card interface enables reception and transmission using the DMAC.
In transmission, when the TDRE flag in SCSSR is set to 1, a DMA transfer request for transmit
data empty is issued. If a DMA transfer request for transmit data empty is set in advance as a
DMAC activation source, the DMAC can be activated and made to transfer data when a DMA
transfer request for transmit data empty occurs.
When in T = 0 mode and if an error signal is received during transmission, the same data is
automatically retransmitted. At the time of this retransmission, no DMA transfer request is issued,
and so the number of bytes specified to the DMAC can be transmitted.
When using the DMAC for transmit data processing and performing error processing as a result of
an interrupt request sent to the CPU, the TIE bit should be cleared to 0 so that no TXI requests are
Rev. 1.00 Oct. 01, 2007 Page 1276 of 1956
REJ09B0256-0100