SH7763 Datasheet, PDF (14/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 10 SuperHyway Bus Bridge (SBR)...................................................... 313
10.1 Features.............................................................................................................................. 313
10.2 Register Descriptions......................................................................................................... 314
10.2.1 Bus Arbitration Priority Level Setting Register (SBRIVCLV) ............................ 315
10.2.2 SuperHyway Bus Priority Control Resister (PRPRICR) ...................................... 316
10.3 Operation ........................................................................................................................... 317
10.3.1 SuperHyway Bus Interface ................................................................................... 317
10.3.2 Bus Arbitration ..................................................................................................... 317
Section 11 Local Bus State Controller (LBSC)................................................. 319
11.1 Features.............................................................................................................................. 319
11.2 Input/Output Pins............................................................................................................... 322
11.3 Area Overview................................................................................................................... 324
11.3.1 Space Divisions .................................................................................................... 324
11.3.2 Memory Bus Width .............................................................................................. 328
11.3.3 Data Alignment..................................................................................................... 329
11.3.4 PCMCIA Support ................................................................................................. 329
11.4 Register Descriptions......................................................................................................... 333
11.4.1 Memory Address Map Select Register (MMSELR)............................................. 334
11.4.2 Bus Control Register (BCR) ................................................................................. 336
11.4.3 CSn Bus Control Register (CSnBCR) .................................................................. 340
11.4.4 CSn Wait Control Register (CSnWCR)................................................................ 346
11.4.5 CSn PCMCIA Control Register (CSnPCR).......................................................... 351
11.5 Operation ........................................................................................................................... 356
11.5.1 Endian/Access Size and Data Alignment.............................................................. 356
11.5.2 Areas..................................................................................................................... 361
11.5.3 SRAM interface .................................................................................................... 365
11.5.4 Burst ROM Interface ............................................................................................ 373
11.5.5 PCMCIA Interface................................................................................................ 375
11.5.6 MPX Interface ...................................................................................................... 386
11.5.7 Byte Control SRAM Interface .............................................................................. 399
11.5.8 Wait Cycles between Accesses............................................................................. 403
11.5.9 Bus Arbitration ..................................................................................................... 405
11.5.10 Master Mode......................................................................................................... 407
11.5.11 Cooperation between Master and Slave................................................................ 408
Section 12 DDR-SDRAM Interface (DDRIF) .................................................. 409
12.1 Features.............................................................................................................................. 409
12.2 Input/Output Pins............................................................................................................... 411
Rev. 1.00 Oct. 01, 2007 Page xiv of lxvi