SH7763 Datasheet, PDF (794/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.8 Timer Start Register (TSTR)
TSTR is a 16-bit readable/writable register that selects TCNT operation/stoppage for channels 0 to
3. TSTR is initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or
module standby.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0











 CST3 CST2 CST1 CST0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Initial
Bit Bit Name Value
15 to 4 
All 0
3
CST3
0
2
CST2
0
1
CST1
0
0
CST0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Counter Start
These bits select operation or stoppage for TCNT.
0: TCNTn count operation is stopped)
1: TCNTn performs count operation
n = 3 to 0
Rev. 1.00 Oct. 01, 2007 Page 728 of 1956
REJ09B0256-0100