SH7763 Datasheet, PDF (406/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
11.4.3 CSn Bus Control Register (CSnBCR)
CSnBCR is a 32-bit readable/writable register that specifies the bus width for area n (n = 0 to 2
and 4 to 6), numbers of wait, setup, and hold cycles to be inserted, burst length, and memory
types.
Some types of memory continue to drive the data bus immediately after the read signal is
inactivated. Therefore, a data bus collision may occur when there is consecutive memory access to
different areas or writing to a memory immediately after reading. This LSI automatically inserts
the number of idle cycles set by CSnBCR to prevent data bus collision. During idle cycles,
corresponding signals CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WE, CE2A, CE2B, and BS
are not asserted and RDWR is in the high state and the data is not driven.
CSnBCR is initialized to H'7777 7770 by a power-on reset or a manual reset.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IWW
IWRWD
IWRWS
IWRRD
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IWRRS
BST
SZ
RDSPL
BW
MPX
TYPE
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
R R/W R/W R/W R/W R/W R/W* R/W* R/W R/W R/W R/W R/W* R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 340 of 1956
REJ09B0256-0100