SH7763 Datasheet, PDF (789/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 16-Bit Timer Pulse Unit (TPU)
20.3.4 Timer Interrupt Enable Registers (TIER)
The TIER registers are 16-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has four TIER registers, one for each channel. The TIER registers are
initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode or module
standby.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0









 TC1EU TC1EV TG1ED TG1EC TG1EB TG1EA
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R/W R/W R/W R/W R/W R/W
Bit Bit Name
15 to 6 
5
TC1EU
4
TC1EV
3
TG1ED
Initial
Value
0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be modified.
Underflow Interrupt Enable
Enables or disables interrupt requests by the TCFU bit when
the TCFU bit in TSR is set to 1 in phase counting mode of
channels 2, and 3 (TCNT underflow).
In channels 0 and 1, bit 5 is reserved. It is always read as 0
and cannot be modified.
0: Interrupt requests by TCFU disabled
1: Interrupt requests by TCFU enabled
Overflow Interrupt Enable
Enables or disables interrupt requests by the TCFV bit when
the TCFV bit in TSR is set to 1 (TCNT overflow).
0: Interrupt requests by TCFV disabled
1: Interrupt requests by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests by the TGFD bit when
the TGFD bit in TSR is set to (TCNT and TGRD compare
match).
0: Interrupt requests by TGFD disabled
1: Interrupt requests by TGFD enabled
Rev. 1.00 Oct. 01, 2007 Page 723 of 1956
REJ09B0256-0100