SH7763 Datasheet, PDF (479/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Table 12.3 Access and Data Alignment in Big Endian Mode (External Bus Width is 32 Bits)
M_D31 to M_D24 M_D23 to M_D16 M_D15 to M_D8 M_D7 to M_D0
Byte access at address 0
Data 7 to 0
Byte access at address 1
Data 7 to 0
Byte access at address 2
Data 7 to 0
Byte access at address 3
Data 7 to 0
Byte access at address 4
Data 7 to 0
Byte access at address 5
Data 7 to 0
Byte access at address 6
Data 7 to 0
Byte access at address 7
Data 7 to 0
Word access at address 0
Data 15 to 8
Data 7 to 0
Word access at address 2
Data 15 to 8
Data 7 to 0
Word access at address 4
Data 15 to 8
Data 7 to 0
Word access at address 6
Data 15 to 8
Data 7 to 0
Longword access at address 0 Data 31 to 24
Data 23 to 16
Data 15 to 8
Data 7 to 0
Longword access at address 4 Data 31 to 24
Data 23 to 16
Data 15 to 8
Data 7 to 0
Quadword access at address 0 Data 63 to 56
(first time: address 0)
Data 55 to 48
Data 47 to 40
Data 39 to 32
Quadword access at address 0 Data 31 to 24
(second time: address 4)
Data 23 to 16
Data 15 to 8
Data 7 to 0
Rev. 1.00 Oct. 01, 2007 Page 413 of 1956
REJ09B0256-0100