SH7763 Datasheet, PDF (570/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
3
TAI
0
SH: R/WC Target-Abort Interrupt
PCI: R
Indicates that a transaction is terminated with a
target-abort when a device other than the PCIC
functions as a bus master.
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
2
MAI
0
SH: R/WC Master-Abort Interrupt
PCI: R
Indicates that a transaction is terminated with a
master-abort when a device other than the PCIC
functions as a bus master.
0: Master-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master-abort interrupt occurs
[Set condition]
When a master-abort interrupt occurs.
1
RDPEI
0
SH: R/WC Read Parity Error Interrupt
PCI: R
The PERR assertion is detected during a data read
when a device other than the PCIC functions as a
bus master.
0: Read parity error interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Read parity error interrupt occurs
[Set condition]
When a read parity error interrupt is detected by the
PERR assertion.
Rev. 1.00 Oct. 01, 2007 Page 504 of 1956
REJ09B0256-0100