SH7763 Datasheet, PDF (660/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
CHCR
RS[3:0]
1000
DMARS ^{DMA Transfer}
Request
DMA Transfer
MID
RID Source
Request Signal
011101 11 SSI1
transmitter
Transmit mode : DMRQ = 1
(Transmit data empty
request)
11 SSI1
receiver
Receive mode : DMRQ = 1
(Receive data is not read)
100000 11 SSI2
transmitter
Transmit mode : DMRQ = 1
(Transmit data empty
request)
11 SSI2
receiver
Receive mode : DMRQ = 1
(Receive data is not read)
100001 11 SSI3
transmitter
Transmit mode : DMRQ = 1
(Transmit data empty
request)
11 SSI3
receiver
Receive mode : DMRQ = 1
(Receive data is not read)
100100 11 MMCIF data FIFO data write request
part transmit
MMCIF data FIFO data read request
part receive
101000 01 SIM
transmitter
TXT (transmit data empty)
10 SIM receiver RXI (receive data full)
Source
Any
SSIRDR
Any
SSIRDR
Any
SSIRDR
Any
DR
Any
SCRDR
101100 01
10
101101 01
10
110000 01
10
110100 11
11
110101 11
11
SIOF0
transmitter
SIOF0
receiver
SIOF1
transmitter
SIOF1
receiver
SIOF2
transmitter
SIOF2
receiver
STIF0
transmitter
STIF0
receiver
STIF1
transmitter
STIF1
receiver
TXI (transmit FIFO data
empty)
RXI (receive data full)
Any
SIRDR0
TXI1 (transmit FIFO data
empty)
RXI (receive FIFO data
empty)
TXI (transmit FIFO data
empty)
RXI (receive FIFO data full)
Any
SIRDR1
Any
SIRDR2
FIFO data write request
Any
FIFO data read request
STI0FIFO0
FIFO data write request
Any
FIFO data read request
STI0FIFO1
Bus
Destination Mode
SSITDR
Cycle
steal
Any
SSITDR
Cycle
steal
Cycle
steal
Any
SSITDR
Cycle
steal
Cycle
steal
Any
DR
Any
SCTDR
Any
SITDR0
Any
SITDR1
Any
SITDR2
Any
STI0FIFO0
Any
STI0FIFO1
Any
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Rev. 1.00 Oct. 01, 2007 Page 594 of 1956
REJ09B0256-0100