SH7763 Datasheet, PDF (996/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.84 Transmit Descriptor Fetch Address Register (TDFAR)
TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor
information from the transmit descriptor. Which transmit descriptor information is used for
processing by the E-DMAC can be recognized by monitoring addresses displayed in this register.
The address from which the E-DMAC is actually fetching a descriptor may be different from the
value read from this register. In the initial setting, set the address of the transmit descriptor at
which transmit processing is to be started.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDFA[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TDFA[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
TDFA[31:0]
Initial
Value R/W Description
All 0 R/W Transmit Descriptor Fetch Address
Writing to these bits during transmission is prohibited.
Rev. 1.00 Oct. 01, 2007 Page 930 of 1956
REJ09B0256-0100