SH7763 Datasheet, PDF (1301/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
(2) Regarding Interrupt Source
The transmit sources and receive sources are signals indicating the SIOF state; after being set, if
the state changes, they are automatically cleared by the SIOF.
When the DMA transfer is used, a DMA transfer request of the FIFO is disabled for one cycle at
the end of that DMA transfer.
(3) Processing when Errors Occur
On occurrence of each of the errors indicated as a status in SISTR, the SIOF performs the
following operations.
• Transmit FIFO underflow (TFUDF)
The immediately preceding transmit data is again transmitted.
• Transmit FIFO overflow (TFOVF)
The contents of the transmit FIFO are protected, and the write operation causing the overflow
is ignored.
• Receive FIFO overflow (RFOVF)
Data causing the overflow is discarded and lost.
• Receive FIFO underflow (RFUDF)
An undefined value is output on the bus.
• FS error (FSERR)
The internal counter is reset according to the signal in which an error occurs.
• Assign error (SAERR)
 If the same slot is assigned to both serial data and control data, the slot is assigned to serial
data.
 If the same slot is assigned to two control data items, data cannot be transferred correctly.
Rev. 1.00 Oct. 01, 2007 Page 1235 of 1956
REJ09B0256-0100