SH7763 Datasheet, PDF (263/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Caches
7.3 Operand Cache Operation
7.3.1 Read Operation
When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is read from a cacheable
area, the cache operates as follows:
1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual
address bits [12:5].
2. The tag read from the each way is compared with bits [28:10] of the physical address resulting
from virtual address translation by the MMU:
• If there is a way whose tag matches and its V bit is 1, see No. 3.
• If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is
selected to replace using the LRU bits is 0, see No. 4.
• If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is
selected to replace using the LRU bits is 1, see No. 5.
3. Cache hit
The data indexed by virtual address bits [4:0] is read from the data field of the cache line on
the hitted way in accordance with the access size. Then the LRU bits are updated to indicate
the hitted way is the latest one.
4. Cache miss (no write-back)
Data is read into the cache line on the way, which is selected to replace, from the physical
address space corresponding to the virtual address. Data reading is performed, using the
wraparound method, in order from the quad-word data(8 bytes) including the cache-missed
data. When the corresponding data arrives in the cache, the read data is returned to the CPU.
While the remaining data on the cache line is being read, the CPU can execute the next
processing. When reading of one line of data is completed, the tag corresponding to the
physical address is recorded in the cache, 1 is written to the V bit and 0 is written to the U bit
on the way. Then the LRU bit is updated to indicate the way is latest one.
Rev. 1.00 Oct. 01, 2007 Page 197 of 1956
REJ09B0256-0100