SH7763 Datasheet, PDF (390/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
2. Can be selectable the polarity (initial state is low active). For details, see section 14,
Direct Memory Access Controller (DMAC).
11.3 Area Overview
11.3.1 Space Divisions
The architecture of this LSI provides a 32-bit virtual address space. The virtual address space is
divided into five areas according to the upper address value. The external memory space indicated
by the remaining 29 address bits is divided into eight areas.
The virtual address can be allocated to any external address using the address translation function
of the MMU. For details, see section 6, Memory Management Unit (MMU). This section
describes the area division of the external address space.
With this LSI, various types of memory or PC cards can be connected to each of the seven areas in
the external address space as shown in table 11.2, and accordingly output the chip select signals
(CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B, CE2A, and CE2B). Area 3 is used for DDR-SDRAM.
CS0 to CS2 are asserted when accessing area 0 to 2, and CS4 to CS6 when accessing area 4 to 6.
When the PCMCIA interface is selected for area 5 or 6, CE2A or CE2B is asserted along with
CS5/CE1A or CS6/CE1B for the bytes to be accessed.
Rev. 1.00 Oct. 01, 2007 Page 324 of 1956
REJ09B0256-0100