SH7763 Datasheet, PDF (171/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
Section 5 Exception Handling
5.1 Summary of Exception Handling
Exception handling processing is handled by a special routine which is executed by a reset,
general exception handling, or interrupt. For example, if the executing instruction ends
abnormally, appropriate action must be taken in order to return to the original program sequence,
or report the abnormality before terminating the processing. The process of generating an
exception handling request in response to abnormal termination, and passing control to a user-
written exception handling routine, in order to support such functions, is given the generic name of
exception handling.
The exception handling in this LSI is of three kinds: resets, general exceptions, and interrupts.
5.2 Register Descriptions
Table 5.1 lists the configuration of registers related exception handling.
Table 5.1 Register Configuration
Register Name
Abbr.
Area 7
R/W P4 Address* Address*
Access Size
TRAPA exception register
TRA
R/W H'FF00 0020
H'1F00 0020 32
Exception event register
EXPEVT R/W H'FF00 0024
H'1F00 0024 32
Interrupt event register
INTEVT R/W H'FF00 0028
H'1F00 0028 32
Note: * P4 is the address when virtual address space P4 area is used. Area 7 is the address
when physical address space area 7 is accessed by using the TLB.
Table 5.2 States of Register in Each Operating Mode
Register Name
TRAPA exception register
Exception event register
Interrupt event register
Abbr.
TRA
EXPEVT
INTEVT
Power-on
Reset
Manual Reset Sleep
Undefined Undefined Retained
H'0000 0000 H'0000 0020 Retained
Undefined Undefined Retained
Standby
Retained
Retained
Retained
Rev. 1.00 Oct. 01, 2007 Page 105 of 1956
REJ09B0256-0100