SH7763 Datasheet, PDF (1387/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.20 Interrupt Status Register 2 (INTSTR2)
INTSTR2 controls the interrupt output of the MMCIF.
FRDYI is set even in the set condition after a clear. To clear FRDYI, disable the flag setting
through FRDYIE in INTCR2.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
CDI
FRDY_
TU
FRDYI
Initial value: 0
0
0
0
0
0
1
0
R/W: R R R R R R/(W)* R R/(W)*
Initial
Bit
Bit Name Value R/W Description
Interrupt
output
7 to 3 —
All 0 R
Reserved
These bits are always read as 0. The write
value should always be 0.
2
CDI
0
R/(W)* Card Identification Flag
FRDY
Identifies insert/pullout of card (variation
between high and low of card identification
signal)
[Setting 1 condition]
When insert/pullout of card is identified
while CDIE = 1.
[Clearing 0 condition]
Write 0 after reading CDI = 1.
1
FRDY_TU 1
R
When the set condition of FRDYI is met
Read value
0: Remaining data in FIFO meets the
assert condition specified by DMACR.
1: Remaining data in FIFO does not meet
the assert condition specified by
DMACR.
0
FRDYI
0
R/(W)* FIFI Ready Completion Flag
FRDY
[Setting 1 condition]
When the DMAEN bit is set while FRDYIE
= 1 and the remaining data in FIFO does
not meet the assert condition specified by
DMACR.
[Clearing 0 condition]
Write 0 after reading FRDYI = 1.
Note: * Cleared by writing 0 after reading 1
Rev. 1.00 Oct. 01, 2007 Page 1321 of 1956
REJ09B0256-0100