SH7763 Datasheet, PDF (585/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(23) PCI I/O Bank Mask Register (PCIIOBMR)
This register specifies the size of the PCI I/O space.
Refer to Section 13.4.3 (2), Accessing PCI Memory Space.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———————————
IOBAMR
——
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R/W R/W R/W R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit
Bit Name
31 to 21 —
Initial
Value
All 0
R/W
SH: R
PCI: 
20 to 18 IOBAMR All 0
SH: R/W
PCI: 
17 to 0 
All 0 SH: R
PCI: 
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI I/O Space Bank Address Mask (3 bits)
000: 256 Kbytes
001: 512 Kbytes
011: 1 Mbyte
111: 2 Mbytes
Other than above: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 519 of 1956
REJ09B0256-0100