SH7763 Datasheet, PDF (1517/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
(2) Transmission using Interrupt Data Flow Control
Start
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable DMA,
enable error interrupts
For n =
( (CHNL + 1) x 2)
Loop
Wait for interrupt
from SSI
Data interrupt?
No
Yes
Load data of channel n
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
Use SSI status register bits
to realign data
after underflow/overflow
Next Channel
Yes
More data
to be send?
No
Disable SSI module,
disable DMA
disable error interrupt,
enable Idle interrupt
Wait for Idle interrupt
from SSI module
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Reset SSI module if required
End
Figure 34.20 Transmission using Interrupt Data Flow Control
Rev. 1.00 Oct. 01, 2007 Page 1451 of 1956
REJ09B0256-0100