SH7763 Datasheet, PDF (1272/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
5
SAERR
0
R/W Slot Assign Error
0: Indicates that no slot assign error occurs
1: Indicates that a slot assign error occurs
A slot assign error occurs when the specifications in
SITDAR, SIRDAR, and SICDAR overlap.
If a slot assign error occurs, the SIOF does not transmit
data to the SIOF_TXD pin and does not receive data
from the SIOF_RXD pin. Note that the SIOF does not
clear the TXE bit or RXE bit in SICTR at a slot assign
error.
• This bit is valid when the TXE bit or RXE bit in
SICTR is 1.
• When 1 is written to this bit, the contents are
cleared.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
4
FSERR
0
R/W Frame Synchronization Error
0: Indicates that no frame synchronization error occurs
1: Indicates that a frame synchronization error occurs
A frame synchronization error occurs when the next
frame synchronization timing appears before the
previous data or control data transfers have been
completed.
If a frame synchronization error occurs, the SIOF
performs transmission or reception for slots that can be
transferred.
• This bit is valid when the TXE or RXE bit in SICTR
is 1.
• When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Rev. 1.00 Oct. 01, 2007 Page 1206 of 1956
REJ09B0256-0100