SH7763 Datasheet, PDF (1652/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 37 LCD Controller (LCDC)
Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit
lines should be connected to GND or to the lowest bit from which data is output.
2. For details, see section 37.4.1, LCD Module Sizes which can be Displayed in this
LCDC.
Figure 37.1 shows a block diagram of LCDC.
LCD_CLK
Bck
Pck0
Peripheral
bus 0
Clock
generator
DOTCLK
Register
LCDC
Pallet RAM
4 bytes × 256 entries
Bus interface
Power control
Line buffer
2.4 Kbytes
DDRIF
DDR I/O
DDR-SDRAM
(VRAM)
Figure 37.1 LCDC Block Diagram
Normal output pin group
LCD_CL1
LCD_CL2
LCD_FLM
LCD_D15 to 0
LCD_DON
LCD_VCPWC
LCD_VEPWC
LCD_M_DISP
Mirror output output group
LCDM_CL1
LCDM_CL2
LCDM_FLM
LCDM_D15 to 0
LCDM_DON
LCDM_VCPWC
LCDM_VEPWC
LCDM_M_DISP
Rev. 1.00 Oct. 01, 2007 Page 1586 of 1956
REJ09B0256-0100