SH7763 Datasheet, PDF (1097/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.3.2 Slave Status Register (ICSSR)
The status bits (bits 0 to 4) in the slave status register are cleared by writing 0 to the respective
status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and
STM bits).
Bit: 7
6
5
4
3
2
1
0
− GCAR STM SSR SDE SDT SDR SAR
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name Initial Value R/W Description
7
—
0
R
Reserved
The write value should always be 0.
6
GCAR
0
R
General Call Address Received
Indicates that the address received from the
bus is a general call address (00H). This status
bit does not cause an interrupt.
This bit is automatically cleared by hardware
when the SIE bit (bit 2 in the slave control
register) is set to 0 or when the SSR bit (bit 4
in this register) is set to 1.
5
STM
0
R
Slave Transmit Mode
Indicates whether the current slave transmit
mode is read or write. When this bit is set to 1,
the mode is read. When this bit is set to 0, the
mode is write. This status bit does not cause
an interrupt.
This bit is automatically cleared by hardware
when the SIE bit (bit 2 in the slave control
register) is set to 0 or when the SSR bit (bit 4
in the slave status register) is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1031 of 1956
REJ09B0256-0100