SH7763 Datasheet, PDF (900/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.22 Automatic PAUSE Frame Register (APR)
APR is used to set the TIME parameter value of an automatic PAUSE frame. When an automatic
PAUSE frame is transmitted, the value set in this register is used as the TIME parameter of the
PAUSE frame.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
AP[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 16 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 0 AP[15:0] All 0 R/W Automatic PAUSE
These bits set the TIME parameter value of an
automatic PAUSE frame. One bit is equivalent to 512
bit-time.
When flow control is enabled in transmission (PAUSE
frame transmission) (TXF bit in ECMR = 1), set a value
other than H'0000 in these bits.
H'0000: 
H'0001: 512 × 1 bit-time
H'0002: 512 × 2 bit-time
:
:
H'FFFF: 512 × 65,535 bit-time
Note:
The bit-time becomes as follows according to
the transfer speed.
1000 Mbps: 1 bit-time = 1 ns
100 Mbps: 1 bit-time = 10 ns
10 Mbps: 1 bit-time = 100 ns
Rev. 1.00 Oct. 01, 2007 Page 834 of 1956
REJ09B0256-0100