SH7763 Datasheet, PDF (10/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

5.3.1 Exception Handling Flow ..................................................................................... 109
5.3.2 Exception Handling Vector Addresses ................................................................. 109
5.4 Exception Types and Priorities .......................................................................................... 110
5.5 Exception Flow .................................................................................................................. 112
5.5.1 Exception Flow..................................................................................................... 112
5.5.2 Exception Source Acceptance............................................................................... 114
5.5.3 Exception Requests and BL Bit ............................................................................ 115
5.5.4 Return from Exception Handling.......................................................................... 115
5.6 Description of Exceptions.................................................................................................. 116
5.6.1 Resets.................................................................................................................... 116
5.6.2 General Exceptions............................................................................................... 118
5.6.3 Interrupts............................................................................................................... 132
5.6.4 Priority Order with Multiple Exceptions .............................................................. 133
5.7 Usage Notes ....................................................................................................................... 135
Section 6 Memory Management Unit (MMU).................................................. 137
6.1 Overview of MMU ............................................................................................................ 137
6.1.1 Address Spaces ..................................................................................................... 140
6.2 Register Descriptions......................................................................................................... 146
6.2.1 Page Table Entry High Register (PTEH).............................................................. 147
6.2.2 Page Table Entry Low Register (PTEL) ............................................................... 148
6.2.3 Translation Table Base Register (TTB) ................................................................ 149
6.2.4 TLB Exception Address Register (TEA) .............................................................. 149
6.2.5 MMU Control Register (MMUCR) ...................................................................... 149
6.2.6 Physical Address Space Control Register (PASCR)............................................. 152
6.2.7 Instruction Re-Fetch Inhibit Control Register (IRMCR) ...................................... 153
6.3 TLB Functions ................................................................................................................... 156
6.3.1 Unified TLB (UTLB) Configuration .................................................................... 156
6.3.2 Instruction TLB (ITLB) Configuration................................................................. 159
6.3.3 Address Translation Method................................................................................. 160
6.4 MMU Functions................................................................................................................. 162
6.4.1 MMU Hardware Management.............................................................................. 162
6.4.2 MMU Software Management ............................................................................... 162
6.4.3 MMU Instruction (LDTLB).................................................................................. 163
6.4.4 Hardware ITLB Miss Handling ............................................................................ 164
6.4.5 Avoiding Synonym Problems............................................................................... 165
6.5 MMU Exceptions............................................................................................................... 166
6.5.1 Instruction TLB Multiple Hit Exception............................................................... 166
6.5.2 Instruction TLB Miss Exception........................................................................... 167
6.5.3 Instruction TLB Protection Violation Exception .................................................. 168
Rev. 1.00 Oct. 01, 2007 Page x of lxvi