SH7763 Datasheet, PDF (402/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Example:
-----------------------------------------------------------------------
MOV.L #H'FE600020, R0
;
MOV.L #MMSELR_DATA, R1
; MMSELR_DATA=Writing value of MMSELR
SYNCO
;
(upper word=H'A5A5)
MOV.L R1, @R0
; Writing to MMSELR
MOV.L @R0, R2
MOV.L @R0, R2
SYNCO
-----------------------------------------------------------------------
Modify executing instruction of MMSELR should allocate non-cacheable P2 area and the address
that should not be affected by address map change.
Write to MMSELR before enable Instruction cache, Operand cache, and MMU address translation
and after this never write again until execute power-on reset or manual reset.
11.4.2 Bus Control Register (BCR)
The bus control register (BCR) is a 32-bit readable/writable register that specifies the function and
bus cycle status for each area. It is initialized to H'0000 0000 in big-endian mode or H'8000 0000
in little-endian mode by a power-on reset or a mammal reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − − − − ^END
IAN
DPUP
OPUP
DACKBST[3:0]
−
− BREQ DMA
EN BST
Initial value: 0/1* 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R/W R R/W R/W R/W R/W R/W R R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − HIZ
CNT
−
−
−
−
−
−
ASYNC[6:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R R R R R R R R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 336 of 1956
REJ09B0256-0100