SH7763 Datasheet, PDF (57/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Tables
Section 1 Overview
Table 1.1 Features of the SH7763........................................................................................... 80
Table 1.2 Pin Configuration.................................................................................................... 94
Section 2 Programming Model
Table 2.1 Initial Register Values............................................................................................. 40
Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 50
Section 3 Instruction Set
Table 3.1 Execution Order of Delayed Branch Instructions ................................................... 57
Table 3.2 Addressing Modes and Effective Addresses........................................................... 59
Table 3.3 Notation Used in Instruction List............................................................................ 64
Table 3.4 Fixed-Point Transfer Instructions ........................................................................... 66
Table 3.5 Arithmetic Operation Instructions .......................................................................... 68
Table 3.6 Logic Operation Instructions .................................................................................. 70
Table 3.7 Shift Instructions..................................................................................................... 71
Table 3.8 Branch Instructions ................................................................................................. 72
Table 3.9 System Control Instructions.................................................................................... 72
Table 3.10 Floating-Point Single-Precision Instructions .......................................................... 75
Table 3.11 Floating-Point Double-Precision Instructions......................................................... 76
Table 3.12 Floating-Point Control Instructions ........................................................................ 76
Table 3.13 Floating-Point Graphics Acceleration Instructions ................................................. 77
Section 4 Pipelining
Table 4.1 Representations of Instruction Execution Patterns.................................................. 80
Table 4.2 Instruction Groups .................................................................................................. 90
Table 4.3 Combination of Preceding and Following Instructions........................................... 93
Table 4.4 Issue Rates and Execution Cycles........................................................................... 95
Section 5 Exception Handling
Table 5.1 Register Configuration.......................................................................................... 105
Table 5.2 States of Register in Each Operating Mode .......................................................... 105
Table 5.3 Exceptions............................................................................................................. 110
Section 6 Memory Management Unit (MMU)
Table 6.1 Register Configuration.......................................................................................... 146
Table 6.2 Register States in Each Processing State .............................................................. 146
Rev. 1.00 Oct. 01, 2007 Page lvii of lxvi