SH7763 Datasheet, PDF (418/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value R/W
26 to 24 SAB
111
R/W
23, 22 PCWA
00
R/W
21, 20 PCWB
00
R/W
Description
Space Property B
Specify the space property of PCMCIA connected to
second half of area 5 or 6.
000: ATA complement mode
001: Dynamic I/O bus sizing
010: 8-bit I/O space
011: 16-bit I/O space
100: 8-bit common memory
101: 16-bit common memory
110: 8-bit attribute memory
111: 16-bit attribute memory
PCMCIA Wait A
Wait cycle for low-speed PCMCIA. The number of wait
cycles specified by these bits is added to the number
designated by CSnWCR.
These bits are valid, when the access area of PCMCIA
interface is first half of area 5 or 6,
00: No wait cycle inserted
01: 15 wait cycles inserted
10: 30 wait cycles inserted
01: 50 wait cycles inserted
PCMCIA Wait B
Wait cycle for low-speed PCMCIA. The number of wait
cycles specified by these bits is added to the number
designated by PCIW.
These bits are valid, when the access area of PCMCIA
interface is second half of area 5 or 6,
00: No wait cycle inserted
01: 15 wait cycles inserted
10: 30 wait cycles inserted
01: 50 wait cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 352 of 1956
REJ09B0256-0100