SH7763 Datasheet, PDF (1474/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
Initial
Bit
Bit Name Value
29
DMATX16 0
28, 27 
All 0
26
TX12_ATOMIC 1
25

0
24
RXDMAL_EN 0
23
TXDMAL_EN 0
22
RXDMAR_EN 0
21
TXDMAR_EN 0
20 to 0 
All 0
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R
Description
16-bit TX DMA Enable
0: Disables 16-bit packed TX DMA mode. Enables the
TXDMAL_EN and TXDMAR_EN settings.
1: Enables 16-bit packed TX DMA mode. Disables the
TXDMAL_EN and TXDMAR_EN settings.
Reserved
Always 0 for read and write.
TX Slot 1 and 2 Atomic Control
0: Transmits TX data in HACCSAR and that in
HACCSDR separately. (Setting prohibited)
1: Transmits TX data in HACCSAR and that in
HACCSDR in the same frame if bit 19 in HACCSAR
is 0 (write). (HACCSAR must be written last.)
Reserved
Always 0 for read and write.
RX DMA Left Enable
0: Disables 20-bit RX DMA for HACPCML.
1: Enables 20-bit RX DMA is for HACPCML.
TX DMA Left Enable
0: Disables 20-bit TX DMA for HACPCML.
1: Enables 20-bit TX DMA for HACPCML.
RX DMA Right Enable
0: Disables 20-bit RX DMA for HACPCMR.
1: Enables 20-bit RX DMA for HACPCMR.
TX DMA Right Enable
0: Disables 20-bit TX DMA for HACPCMR.
1: Enables 20-bit TX DMA for HACPCMR.
Reserved
Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1408 of 1956
REJ09B0256-0100