SH7763 Datasheet, PDF (652/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
1
NMIF
0
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is
set, DMA transfer is disabled even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1.
When the NMI is input, the DMA transfer in progress
can be done in at least one transfer unit. When the
DMAC is not in operational, the NMIF bit is set to 1
even if the NMI interrupt was input.
0: No NMI interrupt
[Clearing condition]
Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
Note: DMA transfer is stopped when an NMI interrupt is
input. After returning from the NMI interrupt
routine, set all channels again, and then start the
DMA transfer.
0
DME
0
R/W DMA Master Enable
Enables or disables DMA transfers on all channels. If
the DME bit and the DE bit in CHCR are set to 1,
transfer is enabled. In this time, all of the bits TE in
CHCR, NMIF, and AE in DMAOR must be 0. If this bit
is cleared during transfer, transfers in all channels are
terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
Note: To abort the DMA transfer when the on-chip
peripheral module request mode is set for any of
the channels specified by DMAOR (channel 0 to
5), clear the DE bit to 0 while the DMA transfer
request from the corresponding peripheral
module is cleared.
Note: * Writing 0 is possible to clear the flag.
Rev. 1.00 Oct. 01, 2007 Page 586 of 1956
REJ09B0256-0100