SH7763 Datasheet, PDF (350/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
INT2B0: Indicates detailed interrupt sources for the TMU.
Module
TMU
Bit
31 to 7
6
5
4
3
2
1
0
Source Function
Description
—
TUNI5
TUNI4
TUNI3
TICPI2
These bits are always read as 0. The Indicates TMU interrupt
write value should always be 0.
sources. This register
TMU channel 5 underflow interrupt
indicates the TMU
interrupt sources even if
TMU channel 4 underflow interrupt mask setting is made in
TMU channel 3 underflow interrupt
the interrupt mask
register for them.
TMU channel 2 input capture interrupt
TUNI2 TMU channel 2 underflow interrupt
TUNI1 TMU channel 1 underflow interrupt
TUNI0 TMU channel 0 underflow interrupt
INT2B1: Indicates detailed interrupt sources for the RTC.
Module
RTC
Bit
31 to 3
2
1
0
Source Function
Description
—
These bits are always read as 0. The Indicates RTC interrupt
write value should always be 0.
sources. This register
CUI
RTC carry interrupt
indicates the RTC
interrupt sources even if
PRI
RTC period interrupt
mask setting is made in
ATI
RTC alarm interrupt
the interrupt mask
register for them.
INT2B2: Indicates detailed interrupt sources for the SCIF.
Module
SCIF1
Bit
31 to 8
7
6
5
4
Source Function
Description
—
TXI1
BRI1
These bits are always read as 0. The
write value should always be 0.
SCIF channel 1 transmit FIFO data
empty interrupt
SCIF channel 1 break interrupt or
overrun error interrupt
Indicates SCIF interrupt
sources. This register
indicates the SCIF
interrupt sources even if
mask setting is made in
the interrupt mask
register for them.
RXI1
SCIF channel 1 receive FIFO data full
interrupt or receive data ready
interrupt
ERI1 SCIF channel 1 receive error interrupt
Rev. 1.00 Oct. 01, 2007 Page 284 of 1956
REJ09B0256-0100