SH7763 Datasheet, PDF (526/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Name
Power-On
Abbreviation Reset
Manual
Reset
Sleep Mode Standby
PCI memory bank mask register 2 PCIMBMR2 H'0000 0000 H'0000 0000 Retained
Retained
PCI I/O bank register
PCIIOBR
H'0000 0000 H'0000 0000 Retained
Retained
PCI I/O bank master register
PCIIOBMR H'0000 0000 H'0000 0000 Retained
Retained
PCI cache snoop control register 0 PCICSCR0 H'0000 0000 H'0000 0000 Retained
Retained
PCI cache snoop control register 1 PCICSCR1 H'0000 0000 H'0000 0000 Retained
Retained
PCI cache snoop address register 0 PCICSAR0 H'0000 0000 H'0000 0000 Retained
Retained
PCI cache snoop address register 1 PCICSAR1 H'0000 0000 H'0000 0000 Retained
Retained
PCI PIO data register
[Legend] x: Undefined
PCIPDR
H'xxxx xxxx H'xxxx xxxx Retained
Retained
13.3.1 PCIC Enable Control Register (PCIECR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
               ENBL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Initial
Bit
Bit Name Value R/W
31 to 1 —
All 0 R
0
ENBL
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Enable Bit.
Enable the PCIC
0: PCIC disable
The access from both the CPU and external PCI
devices to the PCIC is invalid (including the
configuration and local register), except PCIECR.
1: PCIC enable
Rev. 1.00 Oct. 01, 2007 Page 460 of 1956
REJ09B0256-0100