SH7763 Datasheet, PDF (1038/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
(2) Receive Processing in the Case of Multi-Buffer Frame
If an error occurs during reception in the case of a multi-buffer frame where a receive frame is
divided for storage in multiple buffers, the E-DMAC performs the processing shown in figure
23.13.
In the figure, the invalid receive descriptors (with the RACT bit cleared to 0) represent the
successful reception of data to be stored in buffers, and the valid receive descriptors (with the
RACT bit set to 1) represent unreceived buffers. If a frame receive error occurs with a descriptor
shown in the figure, the status is written back to the corresponding descriptor.
If error interrupts are enabled in EESIPR, an interrupt is generated immediately after the write-
back. If there is a new frame receive request, reception is continued from the buffer after that in
which the error occurred.
E-DMAC Inactivates RATC and writes RFE, RFS
Descriptor read
Descriptors
TT TT
A D F F Frame
C L P P Type
TE 10
0 0 1 0 Start
0 0 0 0 Continune
0 0 0 0 Continune
10 00
10 00
10 00
10 00
10 00
11 10
Start of frame
Receive error
occurence
New frame reception
continues from this buffer
Buffer length set
by descriptor
Transmitted data
Untransmitted dara
Figure 23.13 E-DMAC Operation after Receive Error
Rev. 1.00 Oct. 01, 2007 Page 972 of 1956
REJ09B0256-0100