SH7763 Datasheet, PDF (1082/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3.11 Stream Data Receive Operation
(1) DMAC Register Setting
When starting the stream data receive processing, set the following DMAC registers.
• Set the P4 area address for the data register of the transmit/receive FIFO of the STIF in SAR.
• Set the external memory address in DAR.
• Set the DMA transfer count in TCR according to the following equation. Only the value
calculated below should be set.
Transfer count =
(192 bytes + work area byte count)/16 bytes × transmit/receive packet count
• Set H'0001 0001 in TCRB. The upper bits indicate the transfer count until reloading is
performed, and the lower bits indicate the transfer counter value.
• Set H'0E20 5819 in CHCR.*
• Set the module ID and register ID (H'D3 when STIF channel 0 is used and H'D7 when STIF
channel 1 is used) of the transfer request source in the DMARS bits corresponding to the
DMAC channel used.
Note: * When STIF is not used, do not set CHCR.DVMD bit to 1.
Rev. 1.00 Oct. 01, 2007 Page 1016 of 1956
REJ09B0256-0100