SH7763 Datasheet, PDF (737/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Power-Down Mode
18.3.1 Standby Control Register (STBCR)
STBCR is a 32-bit readable/writable register that selects a power-down mode to be entered after a
SLEEP instruction is executed.
STBCR can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−− −− −− −− −− −−− −−−
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − − − − − − − STBY − − − − − − −
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
STBY
0
R/W Standby
Selects whether to enter sleep mode or software standby
mode after a SLEEP instruction is executed.
0: Sleep mode
1: Software standby mode
6 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 671 of 1956
REJ09B0256-0100