SH7763 Datasheet, PDF (1145/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
5
TDFE
1
R/W*¹ Transmit FIFO Data Empty
Indicates that data has been transferred from SCFTDR
to SCTSR, the number of data bytes in SCFTDR has
fallen to or below the transmit trigger data number set
by bits TTRG1 and TTRG0 in SCFCR, and new
transmit data can be written to SCFTDR.
0: A number of transmit data bytes exceeding the
transmit trigger set number have been written to
SCFTDR
[Clearing conditions]
• When transmit data exceeding the transmit trigger
set number is written to SCFTDR after reading
TDFE = 1, and 0 is written to TDFE
• When transmit data exceeding the transmit trigger
set number is written to SCFTDR by the DMAC
1: The number of transmit data bytes in SCFTDR does
not exceed the transmit trigger set number (Initial
value)
4
BRK
0
[Setting conditions]
• Power-on reset or manual reset
• When the number of SCFTDR transmit data bytes
falls to or below the transmit trigger set number as
the result of a transmit operation*³
R/W*¹ Break Detect
Indicates that a receive data break signal has been
detected.
0: A break signal has not been received
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to BRK after reading BRK = 1
1: A break signal has been received*⁴
[Setting condition]
• When data with a framing error is received, followed
by the space "0" level (low level ) for at least one
frame length
Rev. 1.00 Oct. 01, 2007 Page 1079 of 1956
REJ09B0256-0100