SH7763 Datasheet, PDF (904/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.26 PAUSE Frame Receive Counter Register (PFRCR)
PFRCR is a 16-bit counter that indicates the number of times a PAUSE frame is received. This
register is cleared to 0 when it is read.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PFRXC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 16 
15 to 0 PFRXC[15:0]
Initial
Value
All 0
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value
should always be 0.
R PAUSE Frame Receive Count
These bits indicate the number of PAUSE frames
received when flow control is enabled in reception
(RXF bit in ECMR = 1).
Rev. 1.00 Oct. 01, 2007 Page 838 of 1956
REJ09B0256-0100