SH7763 Datasheet, PDF (502/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
12.5.11 Note on Setting Auto-Refresh Interval
The auto-refresh interval is specified by the DRI bits in MIM. If the DRE bit is set to 1 at the same
time as the DRI bits are set, the time until the first auto-refresh is that selected by the value of the
DRI bits before the new setting was made. However, the second and subsequent auto-refresh
intervals take on the value corresponding to the new setting for the DRI bits. To avoid this
situation, clear the DRE bit to 0 when setting the DRI bits. When the DRE bit is subsequently set
to 1, auto-refreshing proceeds with the specified interval from the first round. When writing 1 to
the DRE bit, the previously written cycle number should be set to the DRI bits.
12.5.12 Address Multiplexing
Address multiplexing is performed so that the DDR-SDRAM is connected without the external
address multiplexing circuit according to the setting of the BW bits in MIM and the SPLIT bits in
SDR. Table 12.7 shows the relationship between the DDR-SDRAM bus width and the addresses
that are output to the address pins according to the setting of the SPLIT bits. If a setting not
specified in table 12.7 is used, correct operation is not guaranteed.
Table 12.7 DDR-SDRAM Address Multiplexing (32-Bit Data Bus)
SPLIT[3:0] ROW × COL
M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
128 M bits × 2 0001 12 × 9 ROW 13 12 — — 11 24 23 22 21 20 19 18 17 16 15 14
(8 M × 16-bit × 2)
COL 13 12 — — — AP* — 10 9 8 7 6 5 4 3 2
256 M bits × 2 0011 13 × 9 ROW 13 12 — 11 25 24 23 22 21 20 19 18 17 16 15 14
(16 M × 16-bit × 2)
COL 13 12 — — — AP* — 10 9 8 7 6 5 4 3 2
512 M bits × 2 0100 13 × 10 ROW 13 12 — 26 25 24 23 22 21 20 19 18 17 16 15 14
(32 M × 16-bit × 2)
COL 13 12 — — — AP* 11 10 9 8 7 6 5 4 3 2
1 G bits × 2
0110 14 × 10 ROW 13 12 27 26 25 24 23 22 21 20 19 18 17 16 15 14
(64 M × 16-bit × 2)
COL 13 12 — — — AP* 11 10 9 8 7 6 5 4 3 2
Note: * Auto-precharge
12.5.13 DDR-SDRAM Access Arbitration
(1) Priority Order of Access Arbitration
The DDRIF has the access arbitration function that arbitrates accesses to the DDR-SDRAM
between the CPU and the LCDC. The priority order of the arbitration is divided in the following
two levels.
Rev. 1.00 Oct. 01, 2007 Page 436 of 1956
REJ09B0256-0100