SH7763 Datasheet, PDF (335/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit Bit Name Value
12
CMT
0
11 to 9 —
All 0
8
DMAC 0
7
H-UDI 0
6
—
0
5
WDT
0
4
SCIF1 0
3
SCIF0 0
2
RTC
0
1
TMU1 0
0
TMU0 0
Section 9 Interrupt Controller (INTC)
R/W Function
Description
R
Indicates CMT interrupt source Indicates interrupt
R
This bit is always read as 0. The ^{sources for each}
write value should always be 0. ^{peripheral module}
(INT2A0 is not
R
Indicates DMAC interrupt source _{affected by the state}
R
Indicates H-UDI interrupt source ^{of the interrupt mask}
register).
R
This bit is always read as 0. The
write value should always be 0. ^{0: No interrupts}
R
Indicates WDT interrupt source
1: Interrupts are
generated
R
Indicates SCIF1 interrupt source _{Note: Reading the}
R
Indicates SCIF0 interrupt source
INTEVT code
R
Indicates RTC interrupt source
R
Indicates TMU1 interrupt source
notified to the
CPU directly
can identify
R
Indicates TMU0 interrupt source
interrupt
sources. In this
case, reading
INT2A0 is not
necessary.
9.3.15 Interrupt Source Register 01 (Mask State is not affected) (INT2A01)
INT2A01 (mask state is not affected) is a 32-bit read-only register that indicates interrupt source
modules. Even if interrupt masking is set in the interrupt mask register, INT2A01 indicates a
source module in a corresponding bit (the corresponding interrupt is not generated). If source
indication is not necessary depending on the state of the interrupt mask register, use INT2A11.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−
−−−
− − − − − − ^{SCIF2 USBF}
STIF1 STIF0
USBH
GETH
ER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
15 14
PCC _−
0
0
RR
13 12 11 10 9
8
7
6
− − ^{ADC TPU SIM SIOF2 SIOF1 LCDC}
0
0
0
0
0
0
0
0
RRRRRRRR
Note: * This bit is reserved in the R5S77631.
5
4
3
2
1
0
IIC1
IIC0
SSI3
SSI2
SSI1
SECU
RITY*
0
0
0
0
0
0
RRRRRR
Rev. 1.00 Oct. 01, 2007 Page 269 of 1956
REJ09B0256-0100