SH7763 Datasheet, PDF (1231/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.11 shows an example of the operation for reception in asynchronous mode.
Start
1 bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
Serial data
SCIF_RXD
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
0/1
RDF flag
Detect flaming
error
FER flag
RXI interrupt
request
One frame
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 28.11 Sample SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
28.4.3 Operation in Clocked Synchronous Mode
Clocked synchronous mode, in which data is transmitted or received in synchronization with clock
pulses, is suitable for fast serial communication.
Since the transmitter and receiver are independent units in the SCIF, full-duplex communication
can be achieved by sharing the clock. Both the transmitter and receiver have a 16-stage FIFO
buffer structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer and reception.
Figure 28.12 shows the general format for clocked synchronous communication.
*
Synchronization
clock
Serial data
Don't care
LSB
Bit 0
One unit of transfer data (character or frame)
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
*
MSB
Bit 7
Don't care
Note: * High except in continuous transfer/reciver.
Figure 28.12 Data Format in Clocked Synchronous Communication
Rev. 1.00 Oct. 01, 2007 Page 1165 of 1956
REJ09B0256-0100